A passive backplane architecture allows for the flexibility to swap in and out various subsystems with plug-in and add-on capabilities in a personal computer (PC). The passive-backplane architecture is comprised of a system bus used to interconnect a plug-in subsystem that is a processor and multiple plug-in subsystems with added functionality. This architecture allows the flexibility to add or swap various plug-in subsystems for system repairs, changes, and upgrades with minimum resulting system downtime.
Many systems rely on a local bus system that supports the passive-backplane architecture. For example, a Peripheral Component Interconnect (PCI) local bus has sufficient bandwidth to offer the throughput demanded by the latest PCs, input/output (I/O) devices, and storage devices.
However, the use of PCI as the local bus introduces issues of vendor interoperability and standards. As such, a group of industrial computer product vendors established the PCI Industrial Computer Manufacturers Group (PICMG) to define standards for industrial passive-backplanes that follow the PCI and Industry Standard Architecture (ISA) standards, as well as the central processing unit (CPU) card interface specification. As a result, a comprehensive specification and standard for the passive-backplane architecture was generated that supported both the PCI and ISA input/output (I/O) buses.
One of the issues addressed by the PICMG II standard is hot swapping of plug-in subsystems to the passive backplane architecture. Hot swapping refers to the ability of a subsystem (e.g., a plug-in board) to be removed-from or added-to a host system while the host is fully functional and powered. The biggest challenge in hot swapping occurs when the un-powered subsystem is first inserted into the powered host system. The hot swap activity must not adversely perturb the host power system or otherwise impact other components on the host system.
Hot swap issues arise when discharged storage and bypass capacitors on the hot swapped subsystem must be charged by the host power system. A maximum current rate of change (di/dt) must not be exceeded during this event. For example, the PICMG II standard for low voltage rails on plug-in subsystems specifies that the maximum current rate of change (di/dt) must not exceed 1.5 A/ms.
However, conventional ramp circuits, or voltage regulators implemented on controller chips that deliver power to the plug-in subsystem currently violate the PICMG II current rate of change (di/dt) standard. These conventional ramp circuits implement a pass field effect transistor (FET) that delivers current to the plug-in subsystem, as a load, from a host system.
Prior Art FIG. 1A is a chart 100A illustrating the rate of voltage versus time for an output of the FET in the conventional ramp circuit. The output is coupled to the plug-in subsystem, or load. As seen in Prior Art FIG. 1A, the voltage ramps up from 0 volts to another voltage (e.g., −12 to +12 volts) on a linear ramp once the plug-in subsystem demands power.
In one example, at voltage transition A-110, the voltage seen at the output of the conventional ramp circuit sharply transitions from 0 volts to a positive slope m-115. The voltage ramps up at the slope m-115 until an abrupt transition occurs at the voltage transition B-120. The ramp time between the two transitions typically occurs in the millisecond range, e.g., 20 ms.
At transition B-120, the voltage abruptly transitions from a linear ramp with slope m-115 to a constant 5 volts. These two voltage transitions A-110 and B-120 are the regions where the PICMG II standard for the maximum current rate of change (di/dt) is violated, as will be shown later.
Prior Art FIG. 1B is a chart 100B illustrating the corresponding voltage rate of change (dv/dt) on the output of the conventional ramp circuit. The voltage rate of change is a square wave with a maximum value as determined from Prior Art FIG. 1A of (5 volts/20 ms).
The current affecting the output of the conventional ramp circuit is directly related to the voltage rate of change (dv/dt) of Prior Art FIG. 1B. The current in the output is a constant value times the voltage rate of change (dv/dt). The constant value is the total bypass capacitance associated plug-in subsystem, or load.
If the bypass capacitance is large and/or the voltage rate of change is large, then the current drawn from the backplane power supply by the conventional ramp circuit may violate current specification requirements (e.g., current amplitude or current rate of change). Prior Art FIG. 1C is a chart 100C illustrating the current rate of change (di/dt) affecting the output of the conventional ramp circuit.
The PICMG II standard for the maximum current rate of change (di/dt) can be violated in two regions associated with voltage transition A-110 and voltage transition B-120 of the conventional ramp circuit. In Prior Art FIG. 3C, the current rate of change spikes to a large positive value approaching infinity when associated with the abrupt voltage transition seen at A-110. Similarly, the current rate of change spikes to a large negative number approaching negative infinity when associated with the voltage transition seen at B-120. As a result, these two spikes show that the conventional ramp circuit violates the PICMG II standard of maximum current rate of change.
One prior art solution uses a very large capacitor in the conventional ramp circuit. The large capacitor is used to decrease the voltage ramp rate through the output of the conventional ramp circuit in order to comply with the PICMG II standard maximum current rate of change. This very large capacitor increases the overall length of the voltage ramp which helps to accommodate PICMG II standards. However, the voltage on the output of the conventional ramp circuit remains linear for a longer period of time than necessary. As such, the conventional ramp circuit can overheat. A heat sink and oversized FET used to solve the overheating in the conventional art is too costly both in terms of monetary cost and physical space required, rendering this solution inadequate.
Another prior art approach uses an active control loop that provides a true current source with a linearly increasing current value over the ramp duration. This approach works well to flatten out the current rate of change (di/dt) characteristics during the ramp duration when used with a static resistive load. When driving a static resistive load, the ramp duration is predictable and fully optimized from a FET energy perspective. However, real-life circuitry consists of semiconductors and constant power converters that can have negative resistance characteristics when ramping. This can result in unpredictable ramp times, excessive FET power dissipations, and unrecoverable circuit latching. Additionally, this approach is much more complex and requires a sense resistor and consideration for loop damping.